DSA Studio

Virtual Memory Foundations Checkpoint

Address translation, page offsets, permissions, TLB basics, and page faults.

Get every question correct to pass this checkpoint. You can review feedback, revise your answers, and submit again.

1. A PTE exists with Present=false and Writable=true. A write targets it. What fault takes priority in this model?

Select one answer.

2. With a two-entry LRU TLB, access mapped pages 3,8,3,5. Which page is evicted on the final access?

Select one answer.

3. A TLB miss occurs for a virtual page whose PTE is present and readable. Which result is possible for a read?

Select one answer.

4. With 2048-byte pages, byte address 4103 has what offset within its page?
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